In spring 2018 I was introduced to a small startup, Ascenium Corporation, by Andy Robin who was a board member and acting CEO, and after spending some time at the company I was brought in as the full-time CEO. Ascenium was based Capitola and was focused on building a “continuously reconfigurable” Digital Signal Processor (DSP). The company was at that time technically led by by Robert Mykland, who had founded Ascenium in 2001. I think it is fair to describe Ascenium Corp as a “friends and family” affair. An attractive aspect of the company at that time for me was the enthusiastic group of “super angel” Norwegian investors that had been funding the company. These investors were experienced, lovers of technology, and patient.

Ascenium Corp faced a significant number of issues/challenges. Among them was that the target DSP market was too small (i.e. uninteresting to local VCs) to raise significant amounts of new capital, the architecture assumed the compiler had a “perfect temporal and spatial view of external memory” – which is completely unrealistic for any modern general purpose processor – and it assumed an internal routing topology that would not scale to deep-submicron fabrication technologies due to rapidly increasing metal impedance. The team lacked the real-world silicon valley experience to introduce such a product (chip building is a “grey hair” enterprise, as companies such as Facebook, Google, AMZN, and Microsoft have learned). There were also issues with the company legal and stock structure – for example there was no preferred stock class (I was very surprised to learn the investors held only common shares) – which I wanted to “fix”.

I “rebooted” the company with new money from the existing investors, re-incorporated as Ascenium Inc, revised the stock structure in part so that we could offer Incentive Stock Options (ISOs) to new hires, brought in Tom Chaffin of Pillsbury Winthrop as corporate counsel, and brought in some more experienced patent attorneys (Adams IP), and physically relocated the company into Silicon Valley. I also established a relationship with a PEO (Professional Employer Organization), such as Trinet or ADP, which is crucial for a startup to be able to offer competitive healthcare for recruiting purposes. This was not an issue for the Norwegian team members as socialized medicine there takes care of healthcare.

Ascenium Inc separated with Robert and most of the Capitola employees. I then set about hiring a senior grey hair team who possessed extensive chip development experience in the valley to support a pivot by the company to a much bigger, and fundable product – that being a datacenter host microprocessor that could potentially bypass the patent moat surrounding existing deeply pipelined Out-of-Order x86 machines.

Ascenium Inc had an unusual funding source in the form of a Norwegian Holding Company called Ascenium Holding AS. Ascenium Holding AS had tradable stock, and proceeds raised by Ascenium Holding AS through its stock sales were forwarded to Ascenium Inc, for which Ascenium Holding AS would in return receive preferred stock in Ascenium Inc. Because Ascenium Holding AS stock was “semi” liquid (similar to the US grey market) – that stock maintained a premium over the established valuation of the Ascenium Inc preferred shares. Ascenium Holding AS only asset was preferred stock in Ascenium Inc.

From an architectural perspective, the company pivoted to a general purpose host processor (named Aptos) composed of an homogenous array of small 32-bit Compute Elements that were dynamically reconfigured (including interconnect) every clock cycle by a large losslesly compressed Control Word. Unused Compute Elements could be idled very efficiently by the compiler on a cycle-by-cycle basis (both from a power and Control Word size standpoint). The compiler had perfect knowledge of everything in the array, but once data left the array it entered the external memory domain at which point the compiler could make no exact assumptions. Hence the array itself was statically scheduled, and this approach borrowed some from my previous company, Wave Computing. The array was surrounded on all 4 sides by memory (either data memory or Control Word memory). The array had to stall if a memory fetch did not return in time – and hence there was a significant incentive for the compiler to issue Loads early and maximize data re-use in the array.

To increase parallelism or “IPC” (Instructions Per Cycle equivalent) program loops (for example) could be unrolled and simultaneously “pressed” into the array, where loop variables, including test results, could be rapidly (single cycle) broadcast to all loop instances in the array. When a loop terminated, loop instances in the array that issued stores to external memory “past the end of the loop” would have those stores suppressed before they left the array in order to prevent “side effects”.

As Aptos was statically scheduled, the compiler itself handled both routing and execution in the array. Accomplishing this required aggressive deployment of advanced “compiler” techniques such as constraint programming and/or simulated annealing – techniques that were more commonly used in the silicon EDA world.

Most modern host processor architectures (x86, ARM etc) are “deeply pipelined” and are constrained by key serialization “choke points” such as renamers and register files. Aptos had no pipeline (other than Control Word fetch and decompress), and had no key internal array choke points. The entire array acted as a very large distributed compiler visible register file with massive amounts of configurable inter-array interconnect & bandwidth.

In standard processors, deep pipelines make branch prediction and speculative execution absolutely key to performance. Branch prediction is not necessary in Aptos (there is minimal branch penalty) and the additional power and memory bandwidth required to support speculative execution is not necessary either.

Ascenium filed over 20 patents on the Aptos Architecture during my tenure, where I was the principle inventor on most of them (the patent list is shown below).

In early 2019 I was invited to be a panelist and keynote speaker at ChipEx 2019 in Israel. ChipEx is Israel’s premier semiconductor conference. The Aptos architecture was publicly disclosed for the first time at this conference in May, and my presentation was judged to be the “best in show”. Most of the slides from this presentation are shown below.

Ascenium grew to roughly 22 employees during my tenure as CEO, 10 in Campbell CA (hardware and compiler), 2 in Austin Tx (hardware), 1 in Israel (security), and 9 in Norway (compiler) split between Stavanger and Oslo. Growth was constrained by available funding and a frothy employment market.

Designing and building state of the art processors is not for the faint of heart from a funding perspective. We knew that to be an acquisition target by a large semi company, proof silicon was generally necessary – and we at the time were targeting a 7nm prototype on a TSMC shuttle run. But just the EDA tools and IP alone for such an effort can run 10s of $Mm and the team size would have to grow substantially. To their credit, the investors stepped up and we undertook a concerted effort to raise $80M in Scandinavia in the Spring of 2021. Because of the nature of the fundraise – in the form of a stock offering by Ascenium Holding AS, the process in terms of legal and financial diligence was more like an IPO, Hence local (Norwegian) offices of ABG Sundal, Pareto Securities, Deloitte, PWC. E&Y, Amtzen de Besche, and Schjodt, were all involved. We held numerous team video conference calls, hammered out a pitch, and were about to launch the virtual road show (this was during the pandemic) when, during our last “kickoff” call, the investment bankers said the market had turned and they didn’t think they could “get it done”.

We subsequently closed $16M, mostly from the existing insiders, to continue development – and its a real testament to our insiders for stepping up and raising this smaller round.

Unfortunately in October 2022, the investors felt that the global funding market was such that substantial new funding for the company would be unlikely – so they elected to shut the company down with the exception of the Norwegian compiler team and our employee in Israel focused on security.

Since the vast majority of the “grey hair” processor architecture, silicon and computer systems experience, as well as target market biz dev knowledge was in Silicon Valley – including the CEO, CTO, VP Hardware/Silicon Engineering and VP Business Development – it seemed unlikely to the US team that the company could meaningfully proceed along the lines of anything close to the existing business plan.

Another significant issue is that the existing investors, to my surprise, had earlier informed me they would not accept US Venture Capital investment. The valley VC world is my “back yard” and I am familiar with the local investor community and have worked at both Benchmark Capital as an Entrepreneur in Residence (EIR) and Tallwood Venture Capital as a venture partner and have pitched to many local VCs. When I pointed out the standard valley logic applied to the investor’s position is that 20% of something is a lot better than 80% of nothing – the investors said they could not accept the dilution that they had experienced with US VC investors. They instead preferred strategic investors – but as I pointed out – it is quite difficult/unlikely for semiconductor strategics to invest in a processor startup without proof silicon.

I had been warned by friends before assuming the CEO role at Ascenium to “be careful of European investors” because they “think differently”. But it was their decision to make and their $, and my overall experience with this investor group over the previous 4 years had been quite good.

The US team was let go in November/December ’22 and the Campbell office closed.

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Below are the Patents in flight as of Oct 2024, in the order they were filed, where the Author is a named inventor:

1) Highly Parallel Processing Architecture with Shallow Pipeline (Foley)
2) Parallel Processing Architecture with Background Loads (Foley)
3) Highly Processing Architecture with Compiler (Harboe, Foley, Bastiansen)
4) Highly Parallel Processing Architecture using Dual Branch Execution (Foley)
5) Parallel Processing Architecture using Speculative Encoding (Foley)
6) Parallel Processing Architecture for Atomic Operations (Foley)
7) Parallel Processing Architecture with Distributed Register Files (Foley)
8) Load Latency Amelioration using Bunch Buffers (Foley)
9) Compute Element Processing using Control Word Templates (Hristodorescu, Foley)
10) Highly Parallel Processing Architecture with Out-of-Order Resolution (Foley)
11) Autonomous Compute Element Operation using Buffers (Foley)
12) Parallel Processing of Multiple Loops with Loads and Stores (Foley)
13) Parallel Processing Architecture with Dual Load Buffers (Foley)
14) Parallel Processing Architecture with Memory Block Transfers (Foley)
15) Parallel Processing Architecture with Countdown Tagging (Foley)
16) Parallel Processing Architecture with Split Control Word Caches (Foley)
17) Parallel Processing Architecture with Bin Packing (Foley)
18) Parallel Processing using Hazard Detection and Mitigation (Foley)
19) Parallel Processing with Hazard Detection and Store Probes (Foley)
20) Parallel Processing with Switch Block Execution (Foley)
21) Parallel Processing Architecture for Branch Path Suppression (Foley)
22) Parallel Processing Hazard Mitigation Avoidance (Foley)

One of Ascenium’s investors is a friend of an nVidia Board member- and through that connection I was able to arrange a zoom call in May ’21 with Jen-hsun (founder and CEO of Nvidia). I had prepared for a 1-1 with him, but to my surprise when the meeting launched he was flanked by Chief Scientist Bill Dally and VP CPU Engineering Darrell Boggs. The presence of these two senior staff members substantially changed the tone of the meeting as they were primed with technical due diligence questions.

A notable exchange occurred when Jen-hsun explained their experience with the Denver processor development within Nvidia. Nvidia was of course interested in sourcing its own host processor to bypass Intel, and they acquired the assets and team from Transmeta when that company folded. Transmeta was (like Aptos) also a statically scheduled architecture, but with a traditional pipelined design, and Nvidia improved upon the Transmeta design and built multiple generations of Denver and, as Jen-hsun put it, spent $600M along the way. He said – “it worked, but it wasn’t good enough, so I killed it” and “As a result of that experience I have build high walls – and I don’t think you can do what you are claiming – but I hope I am wrong, and I hope you will come back and explain to me why I am wrong, because then I will be very grateful”. So that then became a highly desirable outcome goal for me to bring to Ascenium’s investors – a “very grateful” Jen-hsun Huang!

Jen-hsun instructed his team to have a follow-up meeting with us to explain “everything we did wrong on Denver” . We held that meeting a week or so later. Dally and Boggs were there, along with Nathan Tuck and Steve Keckler. They were not as forthcoming as they would have been if Jen-hsun were there – but it was a useful meeting nonetheless.